-- Programming Assignment 7 - Single-Datapath Cycle Design -- Ed Yakabosky & Kyle Nase -- Please note that Kyle and Ed spent a LOT of time on this project. We exchanged -- many emails with Krishna and went to his office hours. He can note all of the -- hard work we put into this. Again, we are not experts in the material and -- struggle with the VHDL so this might not work completely correctly but please -- look at the code and take into consideration what we did and how close we might -- have been. Thanks so much. -- Answer to question...The worst case delay is 60ns (instruction memory) + 30 ns -- (register file) + 60 ns (data memory) + 192 ns (ALU) = 342 ns. 1/342 ns = 2.92 -- MHz. Our processor speed is about 2.92 Mhz. --******************** -- Clock --******************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity periodic is port (Z:out std_logic); end entity periodic; architecture behavioral of periodic is begin process is begin Z <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 40 ns; wait for 60 ns; end process; end architecture behavioral; --********************** -- Main Processor --********************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Processor is end Processor; architecture Structural of Processor is component Data_Mem is port(write_data: in std_logic_vector(31 downto 0); addr: in std_logic_vector(6 downto 0); mem_read, mem_write, clock: in std_logic; read_data: out std_logic_vector(31 downto 0)); end component; component periodic is port (Z:out std_logic); end component; component Instr_Mem is port(addr: in std_logic_vector(6 downto 0); read_data: out std_logic_vector(31 downto 0)); end component; component RegFile is port(write_data: in std_logic_vector(31 downto 0); write_addr, read1_addr, read2_addr: in std_logic_vector(4 downto 0); clock, reg_write: in std_logic; read1_data, read2_data: out std_logic_vector(31 downto 0)); end component; component Mux2to1 is port(w0, w1: in std_logic_vector(31 downto 0); s: in std_logic; f: out std_logic_vector(31 downto 0)); end component; component Mux2to1_5input is port (w0, w1: in std_logic_vector(4 downto 0); s: in std_logic; f: out std_logic_vector(4 downto 0)); end component; component Control is port(Op: in std_logic_vector(5 downto 0); RegDst: out std_logic; ALUSrc: out std_logic; MemtoReg: out std_logic; RegWrite: out std_logic; MemRead: out std_logic; MemWrite: out std_logic; Branch: out std_logic; Jump: out std_logic; Extend: out std_logic; ALUop0, ALUop2, aluop3: out std_logic; ALUop1: out std_logic); end component; component ALUControl is port(ALUop0, ALUop1, ALUop2, ALUop3: in std_logic; func: in std_logic_vector (5 downto 0); ALUopOut0, ALUopOut1, ALUopOut2, ALUopOut3: out std_logic); end component; component Program_Counter is port(clk: in std_logic; reset: in std_logic; enable: in std_logic; counterin: in std_logic_vector(31 downto 0); counterout: out std_logic_vector(6 downto 0)); end component; component SignExtend is port(SignIn: in std_logic_vector(15 downto 0); SignOut: out std_logic_vector(31 downto 0)); end component; component ZeroExtend is port(ZeroIn: in std_logic_vector(15 downto 0); ZeroOut: out std_logic_vector(31 downto 0)); end component; component BigAdder is port(A, B: in std_logic_vector (31 downto 0); S: out std_logic_vector (31 downto 0)); end component; component ShiftLeft is port(input : in std_logic_vector(31 downto 0); output : out std_logic_vector(31 downto 0)); end component; component alu32 is port(A, B: in std_logic_vector (31 downto 0); m : in std_logic_vector (3 downto 0); result: out std_logic_vector (31 downto 0); zero, ovf: out std_logic); end component; signal addr: std_logic_vector(6 downto 0); signal read_data: std_logic_vector(31 downto 0); signal counterin: std_logic_vector(31 downto 0); signal SumOne: std_logic_vector(31 downto 0); signal output: std_logic_vector(31 downto 0); signal cookie: std_logic_vector(31 downto 0); signal jump: std_logic; signal RegDst: std_logic; signal ALUSrc: std_logic; signal MemtoReg: std_logic; signal RegWrite: std_logic; signal MemRead: std_logic; signal MemWrite: std_logic; signal Branch: std_logic; signal Extend: std_logic; signal ALUop0, ALUop2, aluop3: std_logic; signal ALUop1: std_logic; signal Yeyo: std_logic_vector(4 downto 0); signal write_data, result: std_logic_vector(31 downto 0); signal clock, enable, reset, zero, overflow : std_logic; signal read1_data, read2_data, SignOut, ZeroOut, MuxOut, Shifted, Added, blammo: std_logic_vector(31 downto 0); signal ALUopOut0, ALUopOut1, ALUopOut2, ALUopOut3, bingo, PCSrc: std_logic; signal output_data : std_logic_vector(31 downto 0); begin clockyclocky: periodic port map(Z=>clock); memory: Instr_Mem port map(addr=>addr,read_data=>read_data); program: Program_Counter port map(clk=>clock, reset=>'0', enable=>'1', counterin=>counterin,counterout=>addr); counterAdder: BigAdder port map(A(31)=>'0', A(30)=>'0', A(29)=>'0', A(28)=>'0', A(27)=>'0', A(26)=>'0', A(25)=>'0', A(24)=>'0', A(23)=>'0', A(22)=>'0', A(21)=>'0', A(20)=>'0', A(19)=>'0', A(18)=>'0', A(17)=>'0', A(16)=>'0', A(15)=>'0', A(14)=>'0', A(13)=>'0', A(12)=>'0', A(11)=>'0', A(10)=>'0', A(9)=>'0', A(8)=>'0', A(7)=>'0', A(6)=>addr(6), A(5)=>addr(5),A(4)=>addr(4),A(3)=>addr(3), A(2)=>addr(2),A(1)=>addr(1),A(0)=>addr(0), B(31)=>'0',B(30)=>'0',B(29)=>'0',B(28)=>'0',B(27)=>'0',B(26)=>'0', B(25)=>'0',B(24)=>'0',B(23)=>'0',B(22)=>'0',B(21)=>'0',B(20)=>'0',B(19)=>'0',B(18)=>'0',B(17)=>'0',B(16)=>'0',B(15)=>'0', B(14)=>'0',B(13)=>'0',B(12)=>'0',B(11)=>'0',B(10)=>'0',B(9)=>'0',B(8)=>'0',B(7)=>'0',B(6)=>'0',B(5)=>'0',B(4)=>'0', B(3)=>'0',B(2)=>'1',B(1)=>'0',B(0)=>'0',S=>SumOne); ShiftLeftOne: ShiftLeft port map(input(31)=>'0', input(30)=>'0',input(29)=>'0',input(28)=>'0',input(27)=>'0', input(26)=>'0',input(25)=>read_data(25), input(24)=>read_data(24), input(23)=>read_data(23), input(22)=>read_data(22), input(21)=>read_data(21), input(20)=>read_data(20), input(19)=>read_data(19), input(18)=>read_data(18), input(17)=>read_data(17), input(16)=>read_data(16), input(15)=>read_data(15), input(14)=>read_data(14), input(13)=>read_data(13), input(12)=>read_data(12), input(11)=>read_data(11), input(10)=>read_data(10), input(9)=>read_data(9), input(8)=>read_data(8), input(7)=>read_data(7), input(6)=>read_data(6), input(5)=>read_data(5), input(4)=>read_data(4), input(3)=>read_data(3), input(2)=>read_data(2), input(1)=>read_data(1), input(0)=>read_data(0),output=>output); MuxOne: Mux2to1 port map(w0(31)=>SumOne(31), w0(30)=>SumOne(30), w0(29)=>SumOne(29), w0(28)=>SumOne(28), w0(27)=>output(27), w0(26)=>output(26), w0(25)=>output(25), w0(24)=>output(24), w0(23)=>output(23), w0(22)=>output(22), w0(21)=>output(21), w0(20)=>output(20), w0(19)=>output(19), w0(18)=>output(18), w0(17)=>output(17), w0(16)=>output(16), w0(15)=>output(15), w0(14)=>output(14), w0(13)=>output(13), w0(12)=>output(12), w0(11)=>output(11), w0(10)=>output(10), w0(9)=>output(9), w0(8)=>output(8), w0(7)=>output(7), w0(6)=>output(6), w0(5)=>output(5), w0(4)=>output(4), w0(3)=>output(3),w0(2)=>output(2),w0(1)=>output(1),w0(0)=>output(0),w1=>cookie,s=>jump,f=>counterin); Controller: Control port map(op(5)=>read_data(31), op(4)=>read_data(30), op(3)=>read_data(29), op(2)=>read_data(28), op(1)=>read_data(27), op(0)=>read_data(26), RegDst=>RegDst, ALUSrc=>ALUSrc, MemtoReg=>MemtoReg, RegWrite=>RegWrite,MemRead=>MemRead,MemWrite=>MemWrite,Branch=>Branch,Jump=>jump, Extend=>Extend,ALUop0=>ALUop0,ALUop1=>ALUop1, aluop2=>aluop2,aluop3=>aluop3); MuxTwo: Mux2to1_5input port map(w0(4)=>read_data(20), w0(3)=>read_data(19), w0(2)=>read_data(18), w0(1)=>read_data(17), w0(0)=>read_data(16), w1(4)=>read_data(15), w1(3)=>read_data(14), w1(2)=>read_data(13), w1(1)=>read_data(12), w1(0)=>read_data(11), s=>RegDst,f=>Yeyo); Register_file: RegFile port map(write_data=>write_data, write_addr(4)=>Yeyo(4), write_addr(3)=>Yeyo(3), write_addr(2)=>Yeyo(2), write_addr(1)=>Yeyo(1), write_addr(0)=>Yeyo(0), read1_addr(4)=>read_data(25), read1_addr(3)=>read_data(24), read1_addr(2)=>read_data(23), read1_addr(1)=>read_data(22), read1_addr(0)=>read_data(21), read2_addr(4)=>read_data(20), read2_addr(3)=>read_data(19), read2_addr(2)=>read_data(18), read2_addr(1)=>read_data(17), read2_addr(0)=>read_data(16), clock=>clock, reg_write=>RegWrite, read1_data=>read1_data, read2_data=>read2_data); Sign_Extend: SignExtend port map(SignIn(15)=>read_data(15), SignIn(14)=>read_data(14), SignIn(13)=>read_data(13), SignIn(12)=>read_data(12), SignIn(11)=>read_data(11), SignIn(10)=>read_data(10), SignIn(9)=>read_data(9), SignIn(8)=>read_data(8), SignIn(7)=>read_data(7), SignIn(6)=>read_data(6), SignIn(5)=>read_data(5), SignIn(4)=>read_data(4), SignIn(3)=>read_data(3), SignIn(2)=>read_data(2), SignIn(1)=>read_data(1), SignIn(0)=>read_data(0), SignOut=>SignOut); Zero_Extend: ZeroExtend port map(ZeroIn(15)=>read_data(15), ZeroIn(14)=>read_data(14), ZeroIn(13)=>read_data(13), ZeroIn(12)=>read_data(12), ZeroIn(11)=>read_data(11), ZeroIn(10)=>read_data(10), ZeroIn(9)=>read_data(9), ZeroIn(8)=>read_data(8), ZeroIn(7)=>read_data(7), ZeroIn(6)=>read_data(6), ZeroIn(5)=>read_data(5), ZeroIn(4)=>read_data(4), ZeroIn(3)=>read_data(3), ZeroIn(2)=>read_data(2), ZeroIn(1)=>read_data(1), ZeroIn(0)=>read_data(0), ZeroOut=>ZeroOut); MuxThree: Mux2to1 port map(w0=>SignOut, w1=>ZeroOut, s=>Extend, f=>MuxOut); ShiftLeftTwo: ShiftLeft port map (input=>MuxOut, output=>Shifted); splitadder: BigAdder port map(A=>SumOne, B=>Shifted, S=>Added); MuxFour: Mux2to1 port map(w0=>SumOne, w1=>Added, s=>PCSrc, f=>cookie); MuxFive: Mux2to1 port map(w0=>read2_data,w1=>MuxOut,s=>ALUSrc,f=>blammo); ALU_Control: ALUControl port map(ALUop0=>ALUop0, ALUop2=>ALUop2, ALUop1=>ALUop1, ALUop3=>ALUop3, func(5)=>read_data(5), func(4)=>read_data(4), func(3)=>read_data(3), func(2)=>read_data(2), func(1)=>read_data(1), func(0)=>read_data(0), ALUopOut0=>ALUopOut0, ALUopOut1=>ALUopOut1, ALUopOut2=>ALUopOut2, ALUopOut3=>ALUopOut3); ALU: alu32 port map(A=>read1_data, B=>blammo, m(3)=>ALUopOut3, m(2)=>ALUopOut2, m(1)=>ALUopOut1, m(0)=>ALUopOut0, result=>result, zero=>zero, ovf=>overflow); bingo <= Branch NAND zero after 2 ns; PCSrc <= bingo NAND bingo after 2 ns; Data_Memory: Data_Mem port map(write_data=>read2_data, addr(6)=>result(6), addr(5)=>result(5), addr(4)=>result(4), addr(3)=>result(3), addr(2)=>result(2), addr(1)=>result(1), addr(0)=>result(0), mem_read=>MemRead, mem_write=>MemWrite,clock=>clock, read_data=>output_data); MuxSix: Mux2to1 port map(w0=>result, w1=>output_data,s=>MemToReg,f=>write_data); end structural; -- ********************************** -- Data Memory -- Writes occur with 0 ns delay when -- Clock goes from 1 to 0 and mem_write is 1 -- Reads occur with 100 ns delay when -- Mem_read is 1 -- ********************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Data_Mem is port(write_data: in std_logic_vector(31 downto 0); addr: in std_logic_vector(6 downto 0); mem_read, mem_write, clock: in std_logic; read_data: out std_logic_vector(31 downto 0)); end Data_Mem; architecture Memory_Behavior of Data_Mem is type mem_array is array(0 to 31) of std_logic_vector (31 downto 0); begin Memory_Process: process(addr, clock) variable data_array: mem_array := ( (X"7fffffff"), (X"00000000"), (X"0000002D"), (X"0000000C"), (X"00000000"), (X"00000000"), (X"00000000"), (X"ffffffff"), (X"aaaaaaaa"), (X"55555555"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000001"), (X"00000002"), (X"00000006"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000")); variable word_addr: integer; begin word_addr := CONV_INTEGER(addr(6 downto 2)); if (clock'event and clock = '0' and mem_write = '1' ) then data_array(word_addr) := write_data; end if; if (mem_read = '1') then read_data <= data_array(word_addr) after 60 ns; end if; end process Memory_Process; end Memory_Behavior; -- ********************************** -- Instruction Memory -- Reads occur with 100 ns delay after the address change -- ********************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Instr_Mem is port(addr: in std_logic_vector(6 downto 0); read_data: out std_logic_vector(31 downto 0)); end Instr_Mem; architecture Memory_Behavior of Instr_Mem is type mem_array is array(0 to 31) of std_logic_vector (31 downto 0); begin Memory_Process: process(addr) variable data_array: mem_array := ( (X"00008020"), (X"8E080000"), (X"21090001"), (X"25090001"), (X"AE090004"), (X"8E0A0008"), (X"8E0B000C"), (X"014B5822"), (X"AE0B0010"), (X"016A602A"), (X"AE0C0014"), (X"290D7FFF"), (X"AE0D0018"), (X"8E0E001C"), (X"8E0F0020"), (X"8E180024"), (X"00005020"), (X"15400009"), (X"01F84825"), (X"AE090028"), (X"370A000A"), (X"AE0A002C"), (X"01F85027"), (X"AE0A0030"), (X"01F85026"), (X"AE0A0034"), (X"08000011"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000"), (X"00000000")); variable word_addr: integer; begin word_addr := CONV_INTEGER(addr(6 downto 2)); read_data <= data_array(word_addr) after 60 ns; end process Memory_Process; end Memory_Behavior; -- *************************** -- Register File -- *************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity RegFile is port(write_data: in std_logic_vector(31 downto 0); write_addr, read1_addr, read2_addr: in std_logic_vector(4 downto 0); clock, reg_write: in std_logic; read1_data, read2_data: out std_logic_vector(31 downto 0)); end RegFile; architecture RegFile_Behavior of RegFile is type reg_array is array(0 to 31) of std_logic_vector (31 downto 0); begin RegFile_Process: process(read1_addr, read2_addr, clock) variable data_array: reg_array := ( (X"00000000"), -- $zero (X"00000000"), -- $at (X"00000000"), -- $v0 (X"00000000"), -- $v1 (X"00000000"), -- $a0 (X"00000000"), -- $a1 (X"00000000"), -- $a2 (X"00000000"), -- $a3 (X"00000000"), -- $t0 (X"00000000"), -- $t1 (X"00000000"), -- $t2 (X"00000000"), -- $t3 (X"00000000"), -- $t4 (X"00000000"), -- $t5 (X"00000000"), -- $t6 (X"00000000"), -- $t7 (X"00000000"), -- $s0 (X"00000000"), -- $s1 (X"00000000"), -- $s2 (X"00000000"), -- $s3 (X"00000000"), -- $s4 (X"00000000"), -- $s5 (X"00000000"), -- $s6 (X"00000000"), -- $s7 (X"00000000"), -- $t8 (X"00000000"), -- $t9 (X"00000000"), -- $k0 (X"00000000"), -- $k1 (X"00000000"), -- $gp (X"00000000"), -- $sp (X"00000000"), -- $fp (X"00000000")); -- $ra variable addrofread1, addrofread2, addrofwrite: integer; begin addrofread1 := CONV_INTEGER(read1_addr); addrofread2 := CONV_INTEGER(read2_addr); addrofwrite := CONV_INTEGER(write_addr); if (clock'event and clock = '0' and reg_write = '1') then if (addrofwrite /= 0) then data_array(addrofwrite) := write_data; end if; end if; read1_data <= data_array(addrofread1) after 30 ns; read2_data <= data_array(addrofread2) after 30 ns; end process RegFile_Process; end RegFile_Behavior; -- ******************* -- Mux_2to1 -- ******************* library IEEE; use IEEE.std_logic_1164.all; entity mux2to1 is port (w0, w1: in std_logic_vector(31 downto 0); s: in std_logic; f: out std_logic_vector(31 downto 0)); end mux2to1; architecture Mux_Behavior of mux2to1 is begin WITH s SELECT f <= w0 WHEN '0', w1 WHEN '1', w0 WHEN others; end Mux_Behavior; -- ******************* -- Mux_2to1_5input -- ******************* library IEEE; use IEEE.std_logic_1164.all; entity mux2to1_5input is port (w0, w1: in std_logic_vector(4 downto 0); s: in std_logic; f: out std_logic_vector(4 downto 0)); end mux2to1_5input; architecture Mux_Behavior of mux2to1_5input is begin WITH s SELECT f <= w0 WHEN '0', w1 WHEN '1', w0 WHEN others; end Mux_Behavior; -- ******************* -- Control unit -- ******************* library IEEE; use IEEE.std_logic_1164.all; entity control is port(Op: in std_logic_vector(5 downto 0); RegDst: out std_logic; ALUSrc: out std_logic; MemtoReg: out std_logic; RegWrite: out std_logic; MemRead: out std_logic; MemWrite: out std_logic; Branch: out std_logic; Jump: out std_logic; Extend: out std_logic; ALUop0: out std_logic; ALUop1, ALUop2, ALUop3: out std_logic); end control; architecture Control_Unit_Behavior of control is signal lw, sw, rtype, beq, jumpthing: std_logic; begin the_proc: process(Op) begin --LW if (Op = "100011") then RegDst <= 'X'; ALUSrc <= '1'; MemtoReg <= '1'; RegWrite <= '1'; MemRead <= '1'; MemWrite <= '0'; Branch <= '0'; ALUOp3 <= '1'; ALUOp2 <= '1'; ALUOp1 <= '0'; ALUOp0 <= '0'; Jump <= '0'; Extend <= '0'; --SW elsif (Op = "101011") then RegDst <= 'X'; ALUSrc <= '1'; MemtoReg <= 'X'; RegWrite <= '0'; MemRead <= '0'; MemWrite <= '1'; Branch <= '0'; ALUOp3 <= '0'; ALUOp2 <= '1'; ALUOp1 <= '0'; ALUOp0 <= '0'; Jump <= '0'; Extend <= '0'; --Bne elsif (Op = "000101") then RegDst <= 'X'; ALUSrc <= '0'; MemtoReg <= 'X'; RegWrite <= '0'; MemRead <= '0'; MemWrite <= '0'; Branch <= '1'; ALUOp3 <= '1'; ALUOp2 <= '1'; ALUOp1 <= '0'; ALUOp0 <= '1'; Jump <= '0'; Extend <= 'X'; --RTYPE elsif (Op = "000000") then RegDst <= '1'; ALUSrc <= '0'; MemtoReg <= '0'; RegWrite <= '1'; MemRead <= '0'; MemWrite <= '0'; Branch <= '0'; ALUOp2 <= '0'; ALUOp1 <= '1'; ALUOp0 <= '0'; Jump <= '0'; Extend <= 'X'; --JUMP elsif (Op = "000010") then RegDst <= 'X'; ALUSrc <= 'X'; MemtoReg <= 'X'; RegWrite <= '0'; MemRead <= '0'; MemWrite <= '0'; Branch <= 'X'; ALUOp2 <= '1'; ALUOp1 <= 'X'; ALUOp0 <= 'X'; Jump <= '1'; Extend <= 'X'; --ADDI elsif (Op = "001000") then RegDst <= 'X'; ALUSrc <= '1'; MemtoReg <= '0'; RegWrite <= '1'; MemRead <= '0'; MemWrite <= '0'; Branch <= '0'; ALUOp3 <= '0'; ALUOp2 <= '1'; ALUOp1 <= '0'; ALUOp0 <= '1'; Jump <= '0'; Extend <= '0'; --ADDIU elsif (Op = "001001") then RegDst <= 'X'; ALUSrc <= '1'; MemtoReg <= '0'; RegWrite <= '1'; MemRead <= '0'; MemWrite <= '0'; Branch <= '0'; ALUOp3 <= '1'; ALUOp2 <= '1'; ALUOp1 <= '1'; ALUOp0 <= '0'; Jump <= '0'; Extend <= '0'; --SLTI elsif (Op = "001010") then RegDst <= 'X'; ALUSrc <= '1'; MemtoReg <= '0'; RegWrite <= '1'; MemRead <= '0'; MemWrite <= '0'; Branch <= '0'; ALUOp3 <= '0'; ALUOp2 <= '1'; ALUOp1 <= '1'; ALUOp0 <= '0'; Jump <= '0'; Extend <= '0'; --ORI elsif (Op = "001101") then RegDst <= 'X'; ALUSrc <= '1'; MemtoReg <= '0'; RegWrite <= '1'; MemRead <= '0'; MemWrite <= '0'; Branch <= '0'; ALUOp3 <= '1'; ALUOp2 <= '1'; ALUOp1 <= '1'; ALUOp0 <= '1'; Jump <= '0'; Extend <= '1'; else RegDst <= 'X'; ALUSrc <= 'X'; MemtoReg <= 'X'; RegWrite <= 'X'; MemRead <= 'X'; MemWrite <= 'X'; Branch <= 'X'; ALUOp2 <= 'X'; ALUOp1 <= 'X'; ALUOp0 <= 'X'; Jump <= 'X'; Extend <= 'X'; end IF; end process the_proc; end Control_Unit_Behavior; -- ************** -- ALU Control -- ************** library IEEE; use IEEE.std_logic_1164.all; entity ALUcontrol is port(ALUop0, ALUop1,ALUop2, ALUop3: in std_logic; func: in std_logic_vector (5 downto 0); ALUopOut0, ALUopOut1, ALUopOut2, ALUopOut3: out std_logic); end ALUcontrol; architecture Behavior of ALUcontrol is signal temp1, temp2, temp3, temp4, temp5, temp6, temp7: std_logic; signal nand1, nand2, nand3, nand4, nand5, nand6, nand7, nand8, nand9, nand10, nand11, nand12, nand13, nand14, nand15, nand16: std_logic; begin proc_pick: process(ALUOp2) begin if (ALUOp2 = '0') then if (func = "100000") then -- add ALUopOut0 <= '0'; ALUopOut1 <= '1'; ALUopOut2 <= '1'; ALUopOut3 <= '0'; elsif (func = "100010") then -- sub ALUopOut0 <= '0'; ALUopOut1 <= '1'; ALUopOut2 <= '1'; ALUopOut3 <= '1'; elsif (func = "100100") then -- and ALUopOut0 <= '0'; ALUopOut1 <= '0'; ALUopOut2 <= '0'; ALUopOut3 <= '0'; elsif (func = "100101") then -- or ALUopOut0 <= '1'; ALUopOut1 <= '0'; ALUopOut2 <= '0'; ALUopOut3 <= '0'; elsif (func = "100110") then -- xor ALUopOut0 <= '0'; ALUopOut1 <= '1'; ALUopOut2 <= '0'; ALUopOut3 <= '0'; elsif (func = "100111") then -- nor ALUopOut0 <= '1'; ALUopOut1 <= '1'; ALUopOut2 <= '0'; ALUopOut3 <= '0'; elsif (func = "101010") then -- slt ALUopOut0 <= '1'; ALUopOut1 <= '1'; ALUopOut2 <= '1'; ALUopOut3 <= '1'; else -- jump and such ALUopOut0 <= 'X'; ALUopOut1 <= 'X'; ALUopOut2 <= 'X'; ALUopOut3 <= 'X'; end if; elsif (ALUOp3 = '1' AND ALUOp1 = '0' AND ALUOp0 = '0') then -- lw ALUopOut0 <= '0'; ALUopOut1 <= '1'; ALUopOut2 <= '1'; ALUopOut3 <= '0'; elsif (ALUOp3 = '0' AND ALUOp1 = '0' AND ALUOp0 = '0') then -- sw ALUopOut0 <= '0'; ALUopOut1 <= '1'; ALUopOut2 <= '1'; ALUopOut3 <= '0'; elsif (ALUOp3 = '1' AND ALUOp1 = '0' AND ALUOp0 = '1') then -- bne ALUopOut0 <= '0'; ALUopOut1 <= '1'; ALUopOut2 <= '1'; ALUopOut3 <= '1'; elsif (ALUOp3 = '0' AND ALUOp1 = '0' AND ALUOp0 = '1') then -- addi ALUopOut0 <= '0'; ALUopOut1 <= '1'; ALUopOut2 <= '1'; ALUopOut3 <= '0'; elsif (ALUOp3 = '1' AND ALUOp1 = '1' AND ALUOp0 = '0') then -- addiu ALUopOut0 <= '0'; ALUopOut1 <= '1'; ALUopOut2 <= '1'; ALUopOut3 <= '0'; elsif (ALUOp3 = '0' AND ALUOp1 = '1' AND ALUOp0 = '0') then -- slti ALUopOut0 <= '1'; ALUopOut1 <= '1'; ALUopOut2 <= '1'; ALUopOut3 <= '1'; elsif (ALUOp3 = '1' AND ALUOp1 = '1' AND ALUOp0 = '1') then -- ori ALUopOut0 <= '1'; ALUopOut1 <= '0'; ALUopOut2 <= '0'; ALUopOut3 <= '0'; else ALUopOut0 <= 'X'; ALUopOut1 <= 'X'; ALUopOut2 <= 'X'; ALUopOut3 <= 'X'; end if; end process proc_pick; end Behavior; -- ***************** -- Zero Extend -- ***************** library IEEE; use IEEE.std_logic_1164.all; entity ZeroExtend is port(ZeroIn: in std_logic_vector(15 downto 0); ZeroOut: out std_logic_vector(31 downto 0)); end ZeroExtend; architecture Behavior of ZeroExtend is begin ZeroOut(0) <= ZeroIn(0); ZeroOut(1) <= ZeroIn(1); ZeroOut(2) <= ZeroIn(2); ZeroOut(3) <= ZeroIn(3); ZeroOut(4) <= ZeroIn(4); ZeroOut(5) <= ZeroIn(5); ZeroOut(6) <= ZeroIn(6); ZeroOut(7) <= ZeroIn(7); ZeroOut(8) <= ZeroIn(8); ZeroOut(9) <= ZeroIn(9); ZeroOut(10) <= ZeroIn(10); ZeroOut(11) <= ZeroIn(11); ZeroOut(12) <= ZeroIn(12); ZeroOut(13) <= ZeroIn(13); ZeroOut(14) <= ZeroIn(14); ZeroOut(15) <= ZeroIn(15); ZeroOut(16) <= '0'; ZeroOut(17) <= '0'; ZeroOut(18) <= '0'; ZeroOut(19) <= '0'; ZeroOut(20) <= '0'; ZeroOut(21) <= '0'; ZeroOut(22) <= '0'; ZeroOut(23) <= '0'; ZeroOut(24) <= '0'; ZeroOut(25) <= '0'; ZeroOut(26) <= '0'; ZeroOut(27) <= '0'; ZeroOut(28) <= '0'; ZeroOut(29) <= '0'; ZeroOut(30) <= '0'; ZeroOut(31) <= '0'; end Behavior; -- ***************** -- Sign Extend -- ****************** library IEEE; use IEEE.std_logic_1164.all; entity SignExtend is port(SignIn: in std_logic_vector(15 downto 0); SignOut: out std_logic_vector(31 downto 0)); end SignExtend; architecture Behavior of SignExtend is begin SignOut(0) <= SignIn(0); SignOut(1) <= SignIn(1); SignOut(2) <= SignIn(2); SignOut(3) <= SignIn(3); SignOut(4) <= SignIn(4); SignOut(5) <= SignIn(5); SignOut(6) <= SignIn(6); SignOut(7) <= SignIn(7); SignOut(8) <= SignIn(8); SignOut(9) <= SignIn(9); SignOut(10) <= SignIn(10); SignOut(11) <= SignIn(11); SignOut(12) <= SignIn(12); SignOut(13) <= SignIn(13); SignOut(14) <= SignIn(14); SignOut(15) <= SignIn(15); SignOut(16) <= SignIn(15); SignOut(17) <= SignIn(15); SignOut(18) <= SignIn(15); SignOut(19) <= SignIn(15); SignOut(20) <= SignIn(15); SignOut(21) <= SignIn(15); SignOut(22) <= SignIn(15); SignOut(23) <= SignIn(15); SignOut(24) <= SignIn(15); SignOut(25) <= SignIn(15); SignOut(26) <= SignIn(15); SignOut(27) <= SignIn(15); SignOut(28) <= SignIn(15); SignOut(29) <= SignIn(15); SignOut(30) <= SignIn(15); SignOut(31) <= SignIn(15); end Behavior; -- ******************** -- Program Counter -- ******************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity Program_counter is port (clk: in std_logic; reset: in std_logic; enable: in std_logic; counterin: in std_logic_vector(31 downto 0); counterout: out std_logic_vector(6 downto 0)); end Program_Counter; architecture behav of program_counter is begin process(clk) begin if (clk='1' and clk'event) then counterout(6) <= counterin(6); counterout(5) <= counterin(5); counterout(4) <= counterin(4); counterout(3) <= counterin(3); counterout(2) <= counterin(2); counterout(1) <= counterin(1); counterout(0) <= counterin(0); end if; end process; end behav; -- ********************* -- Shift Left 2 -- ********************* library IEEE; use IEEE.std_logic_1164.all; entity Shift_Left is port (input: in std_logic_vector(31 downto 0); output: out std_logic_vector(31 downto 0)); end Shift_Left; architecture Behavior of Shift_Left is begin output(31)<=input(29); output(30)<=input(28); output(29)<=input(27); output(28)<=input(26); output(27)<=input(25); output(26)<=input(24); output(25)<=input(23); output(24)<=input(22); output(23)<=input(21); output(22)<=input(20); output(21)<=input(19); output(20)<=input(18); output(19)<=input(17); output(18)<=input(16); output(17)<=input(15); output(16)<=input(14); output(15)<=input(13); output(14)<=input(12); output(13)<=input(11); output(12)<=input(10); output(11)<=input(9); output(10)<=input(8); output(9)<=input(7); output(8)<=input(6); output(7)<=input(5); output(6)<=input(4); output(5)<=input(3); output(4)<=input(2); output(3)<=input(1); output(2)<=input(0); output(1)<='0'; output(0)<='0'; end Behavior; -- ************** -- Full Adder -- ************** library IEEE; use IEEE.std_logic_1164.all; entity Full_Adder is port (Cin, A, B: in std_logic; S, Cout: out std_logic); end Full_Adder; architecture Behavior of Full_Adder is signal Temp1, Temp2, Temp11, Temp22, Temp4, Temp5, tempX: std_logic; begin tempX <= (A xor B) after 3 ns; S <= (TempX xor Cin) after 3 ns; Temp1 <= (A nand B) after 2 ns; Temp2 <= (TempX nand Cin) after 2 ns; Temp11 <= (Temp1 nand Temp1) after 2 ns; Temp22 <= (Temp2 nand Temp2) after 2 ns; Temp4 <= (TEMP11 nand TEMP11) after 2 ns; Temp5 <= (TEMP22 nand TEMP22) after 2 ns; Cout <= (Temp4 nand Temp5) after 2 ns; end Behavior; -- ****************** -- 32 bit adder -- ****************** library IEEE; use IEEE.std_logic_1164.all; entity Big_Adder is port (A, B: in std_logic_vector (31 downto 0); S: out std_logic_vector (31 downto 0)); end Big_Adder; architecture Behavior of Big_Adder is component Full_Adder is port (Cin, A, B: in std_logic; S, cout: out std_logic); end component; signal cout : std_logic_vector(31 downto 0); begin bit0: Full_Adder port map(A=>A(0), B=>B(0), cin=>'0',S=>S(0),Cout=>Cout(0)); bit1: Full_Adder port map(A=>A(1), B=>B(1), cin=>cout(0),S=>S(1),Cout=>Cout(1)); bit2: Full_Adder port map(A=>A(2), B=>B(2), cin=>cout(1),S=>S(2),Cout=>Cout(2)); bit3: Full_Adder port map(A=>A(3), B=>B(3), cin=>cout(2),S=>S(3),Cout=>Cout(3)); bit4: Full_Adder port map(A=>A(4), B=>B(4), cin=>cout(3),S=>S(4),Cout=>Cout(4)); bit5: Full_Adder port map(A=>A(5), B=>B(5), cin=>cout(4),S=>S(5),Cout=>Cout(5)); bit6: Full_Adder port map(A=>A(6), B=>B(6), cin=>cout(5),S=>S(6),Cout=>Cout(6)); bit7: Full_Adder port map(A=>A(7), B=>B(7), cin=>cout(6),S=>S(7),Cout=>Cout(7)); bit8: Full_Adder port map(A=>A(8), B=>B(8), cin=>cout(7),S=>S(8),Cout=>Cout(8)); bit9: Full_Adder port map(A=>A(9), B=>B(9), cin=>cout(8),S=>S(9),Cout=>Cout(9)); bit10: Full_Adder port map(A=>A(10), B=>B(10), cin=>cout(9),S=>S(10),Cout=>Cout(10)); bit11: Full_Adder port map(A=>A(11), B=>B(11), cin=>cout(10),S=>S(11),Cout=>Cout(11)); bit12: Full_Adder port map(A=>A(12), B=>B(12), cin=>cout(11),S=>S(12),Cout=>Cout(12)); bit13: Full_Adder port map(A=>A(13), B=>B(13), cin=>cout(12),S=>S(13),Cout=>Cout(13)); bit14: Full_Adder port map(A=>A(14), B=>B(14), cin=>cout(13),S=>S(14),Cout=>Cout(14)); bit15: Full_Adder port map(A=>A(15), B=>B(15), cin=>cout(14),S=>S(15),Cout=>Cout(15)); bit16: Full_Adder port map(A=>A(16), B=>B(16), cin=>cout(15),S=>S(16),Cout=>Cout(16)); bit17: Full_Adder port map(A=>A(17), B=>B(17), cin=>cout(16),S=>S(17),Cout=>Cout(17)); bit18: Full_Adder port map(A=>A(18), B=>B(18), cin=>cout(17),S=>S(18),Cout=>Cout(18)); bit19: Full_Adder port map(A=>A(19), B=>B(19), cin=>cout(18),S=>S(19),Cout=>Cout(19)); bit20: Full_Adder port map(A=>A(20), B=>B(20), cin=>cout(19),S=>S(20),Cout=>Cout(20)); bit21: Full_Adder port map(A=>A(21), B=>B(21), cin=>cout(20),S=>S(21),Cout=>Cout(21)); bit22: Full_Adder port map(A=>A(22), B=>B(22), cin=>cout(21),S=>S(22),Cout=>Cout(22)); bit23: Full_Adder port map(A=>A(23), B=>B(23), cin=>cout(22),S=>S(23),Cout=>Cout(23)); bit24: Full_Adder port map(A=>A(24), B=>B(24), cin=>cout(23),S=>S(24),Cout=>Cout(24)); bit25: Full_Adder port map(A=>A(25), B=>B(25), cin=>cout(24),S=>S(25),Cout=>Cout(25)); bit26: Full_Adder port map(A=>A(26), B=>B(26), cin=>cout(25),S=>S(26),Cout=>Cout(26)); bit27: Full_Adder port map(A=>A(27), B=>B(27), cin=>cout(26),S=>S(27),Cout=>Cout(27)); bit28: Full_Adder port map(A=>A(28), B=>B(28), cin=>cout(27),S=>S(28),Cout=>Cout(28)); bit29: Full_Adder port map(A=>A(29), B=>B(29), cin=>cout(28),S=>S(29),Cout=>Cout(29)); bit30: Full_Adder port map(A=>A(30), B=>B(30), cin=>cout(29),S=>S(30),Cout=>Cout(30)); bit31: Full_Adder port map(A=>A(31), B=>B(31), cin=>cout(30),S=>S(31),Cout=>Cout(31)); end Behavior; -- ***************** -- ALU: 1-Byte Adder -- ***************** library IEEE; use IEEE.std_logic_1164.all; entity alu_1b is port(a, b, c_in: in std_logic; op_in : in std_logic_vector (3 downto 0); c_out, result :out std_logic); end entity alu_1b; architecture beha_alu_1b of alu_1b is signal s1, s2, s3, s4, s5, s6, s7, s8, sum, as_in : std_logic ; begin s4 <= (as_in xor b) after 3ns; --add/sub line going to FA b s1 <= (a xor s4) after 3ns; --FA internal1 s2 <= not(c_in nand s1) after 3ns; s3 <= not(a nand s4) after 3ns; sum <= (s1 xor c_in) after 3ns; c_out <= not(s2 nor s3) after 3ns; s5 <= not(a nand b) after 3ns; --and gate s6 <= not(a nor b) after 3ns; -- OR gate s7 <= (a xor b) after 3ns; --XOR gate s8 <= (a nor b) after 2ns; result <= sum when op_in ="0000" else --ADD sum when op_in ="0001" else --ADDU sum when op_in ="0010" else --SUB sum when op_in ="0011" else --SUBU s5 when op_in ="0100" else --AND s6 when op_in ="0101" else --OR s7 when op_in ="0110" else --XOR s8 when op_in ="0111" else --NOR sum when op_in = "1010" else --SLT changed from less_in sum when op_in = "1011"; --SLTU changed from less_in as_in <= '1' when op_in = "0010" else '1' when op_in = "0011" else '1' when op_in = "1010" else '1' when op_in = "1011" else '0'; end architecture beha_alu_1b; -- ********************* -- ALU: 1-Byte MSB -- ********************* library IEEE; use IEEE.std_logic_1164.all; entity alu_1b_msb is port(a, b, c_in : in std_logic; op_in : in std_logic_vector (3 downto 0); c_out, result, overflow, less_out :out std_logic); end entity alu_1b_msb; architecture beha_alu_1b_msb of alu_1b_msb is signal s1, s2, s3, s4, s5, s6, s7, s8, sum, s9, oflow_enable, oflow_detect, as_in, c_out_u, sum_u : std_logic ; begin s4 <= (as_in xor b) after 3ns; --add/sub line going to FA b s1 <= (a xor s4) after 3ns; --FA internal1 s2 <= not(c_in nand s1) after 3ns; s3 <= not(a nand s4) after 3ns; sum <= (s1 xor c_in) after 3ns; c_out <= not(s2 nor s3) after 3ns; s9 <= not(s2 nor s3) after 3ns; -- same as c_out (but internal) s5 <= not(a nand b) after 3ns; --and gate s6 <= not(a nor b) after 3ns; -- OR gate s7 <= (a xor b) after 3ns; --XOR gate s8 <= (a nor b) after 2ns; result <= sum when op_in ="0000" else --ADD sum when op_in ="0001" else --ADDU sum when op_in ="0010" else --SUB sum when op_in ="0011" else --SUBU s5 when op_in ="0100" else --AND s6 when op_in ="0101" else --OR s7 when op_in ="0110" else --XOR s8 when op_in ="0111" else --NOR sum when op_in = "1010" else --SLT changed from less_in sum when op_in = "1011"; --SLTU changed from less_in as_in <= '1' when op_in = "0010" else '1' when op_in = "0011" else '1' when op_in = "1010" else '1' when op_in = "1011" else '0'; oflow_enable <= '1' when op_in ="0000" else '1' when op_in ="0010" else '1' when op_in ="1010" else '0'; oflow_detect <= (c_in xor s9) after 3ns; overflow <= not (oflow_enable nand oflow_detect) after 3ns; end architecture beha_alu_1b_msb; -- ************************* -- ALU: 8-Byte block -- ************************* library IEEE; use IEEE.std_logic_1164.all; entity alu_8b is port(a, b : in std_logic_vector (7 downto 0); c_in: in std_logic; op : in std_logic_vector (3 downto 0); r : out std_logic_vector (7 downto 0); c_out, overflow, zero_detect : out std_logic); end alu_8b; architecture structural of alu_8b is component alu_1b is port(a, b, c_in : in std_logic; op_in : in std_logic_vector (3 downto 0); c_out, result :out std_logic); end component; component alu_1b_msb is port(a, b, c_in : in std_logic; op_in : in std_logic_vector (3 downto 0); c_out, result, overflow :out std_logic); end component; for all: alu_1b use entity work.alu_1b(beha_alu_1b); for all: alu_1b_msb use entity work.alu_1b_msb(beha_alu_1b_msb); signal c_out_int : std_logic_vector (6 downto 0); signal zero_detect_int : std_logic_vector (7 downto 0); signal result_int : std_logic_vector (7 downto 0); signal s1, s2, s3, s4, s5, s6, s7 : std_logic; signal zero_detect_0_1_nor, zero_detect_2_3_nor,zero_detect_4_5_nor,zero_detect_6_7_nor, zero_detect_0_1_or,zero_detect_2_3_or, zero_detect_4_5_or, zero_detect_6_7_or, zero_detect_0_1_2_3_nor,zero_detect_4_5_6_7_nor, zero_detect_0_1_2_3_or,zero_detect_4_5_6_7_or, zero_detect_nor :std_logic; begin EX0: alu_1b port map(a=>a(0), b=>b(0), c_in=>c_in, c_out=>c_out_int(0), op_in=>op, result=>result_int(0)); EX1: alu_1b port map(a=>a(1), b=>b(1), c_in=>c_out_int(0), c_out=>c_out_int(1), op_in=>op, result=>result_int(1)); EX2: alu_1b port map(a=>a(2), b=>b(2), c_in=>c_out_int(1), c_out=>c_out_int(2), op_in=>op, result=>result_int(2)); EX3: alu_1b port map(a=>a(3), b=>b(3), c_in=>c_out_int(2), c_out=>c_out_int(3), op_in=>op, result=>result_int(3)); EX4: alu_1b port map(a=>a(4), b=>b(4), c_in=>c_out_int(3), c_out=>c_out_int(4), op_in=>op, result=>result_int(4)); EX5: alu_1b port map(a=>a(5), b=>b(5), c_in=>c_out_int(4), c_out=>c_out_int(5), op_in=>op, result=>result_int(5)); EX6: alu_1b port map(a=>a(6), b=>b(6), c_in=>c_out_int(5), c_out=>c_out_int(6), op_in=>op, result=>result_int(6)); EX7: alu_1b_msb port map(a=>a(7), b=>b(7), c_in=>c_out_int(6), c_out=>c_out, op_in=>op, result=>result_int(7), overflow=>overflow); r<= result_int; --remap internal result to output port --zero_detect <= (result_int(0) or result_int(1) or result_int(2) or result_int(3) or result_int(4) or result_int(5) or result_int(6) or result_int(7)) after 22ns; --zero detect for 8 bit zero_detect_0_1_nor <= (result_int(0) nor result_int(1)) after 2 ns; zero_detect_2_3_nor <= (result_int(2) nor result_int(3)) after 2 ns; zero_detect_4_5_nor <= (result_int(4) nor result_int(5)) after 2 ns; zero_detect_6_7_nor <= (result_int(6) nor result_int(7)) after 2 ns; zero_detect_0_1_or <= (zero_detect_0_1_nor nor zero_detect_0_1_nor) after 2 ns; zero_detect_2_3_or <= (zero_detect_2_3_nor nor zero_detect_2_3_nor) after 2 ns; zero_detect_4_5_or <= (zero_detect_4_5_nor nor zero_detect_4_5_nor) after 2 ns; zero_detect_6_7_or <= (zero_detect_6_7_nor nor zero_detect_6_7_nor) after 2 ns; zero_detect_0_1_2_3_nor <= (zero_detect_0_1_or nor zero_detect_2_3_or) after 2 ns; zero_detect_0_1_2_3_or <= (zero_detect_0_1_2_3_nor nor zero_detect_0_1_2_3_nor) after 2 ns; zero_detect_4_5_6_7_nor <= (zero_detect_4_5_or nor zero_detect_6_7_or) after 2 ns; zero_detect_4_5_6_7_or <= (zero_detect_4_5_6_7_nor nor zero_detect_4_5_6_7_nor) after 2 ns; zero_detect_nor <= (zero_detect_0_1_2_3_or nor zero_detect_4_5_6_7_or) after 2 ns; zero_detect <= (zero_detect_nor nor zero_detect_nor) after 2 ns; end structural; -- ************************ -- ALU: 32 bit ALU -- ************************ library IEEE; use IEEE.std_logic_1164.all; entity alu32 is port(A, B : in std_logic_vector (31 downto 0); m : in std_logic_vector (3 downto 0); result : out std_logic_vector (31 downto 0); zero, ovf : out std_logic); end alu32; architecture alu32_structure of alu32 is component alu_8b is port(a, b : in std_logic_vector (7 downto 0); c_in : in std_logic; op : in std_logic_vector (3 downto 0); r : out std_logic_vector (7 downto 0); c_out, overflow, zero_detect : out std_logic); end component; for all: alu_8b use entity work.alu_8b(structural); signal c_out_int : std_logic_vector (2 downto 0); signal r_int : std_logic_vector (31 downto 0); signal zero_detect_int : std_logic_vector (3 downto 0); signal slt_internal : std_logic; signal c_in_int : std_logic; signal s1, s2 : std_logic; signal zero_detect_0_1_nor, zero_detect_2_3_nor, zero_detect_0_1_or,zero_detect_2_3_or :std_logic; begin EX0: alu_8b port map(a=>A(7 downto 0), b=>B(7 downto 0), c_in=>c_in_int, c_out=>c_out_int(0), op=>m, r=>r_int(7 downto 0), zero_detect=>zero_detect_int(0)); EX1: alu_8b port map(a=>A(15 downto 8), b=>B(15 downto 8), c_in=>c_out_int(0), c_out=>c_out_int(1), op=>m, r=>r_int(15 downto 8), zero_detect=>zero_detect_int(1)); EX2: alu_8b port map(a=>A(23 downto 16), b=>B(23 downto 16), c_in=>c_out_int(1), c_out=>c_out_int(2), op=>m, r=>r_int(23 downto 16), zero_detect=>zero_detect_int(2)); EX3: alu_8b port map(a=>A(31 downto 24), b=>B(31 downto 24), c_in=>c_out_int(2), op=>m, r=>r_int(31 downto 24), overflow=>ovf, zero_detect=>zero_detect_int(3)); zero_detect_0_1_nor <= (zero_detect_int(0) nor zero_detect_int(1)) after 2 ns; zero_detect_2_3_nor <= (zero_detect_int(2) nor zero_detect_int(3)) after 2 ns; zero_detect_0_1_or <= (zero_detect_0_1_nor nor zero_detect_0_1_nor) after 2 ns; zero_detect_2_3_or <= (zero_detect_2_3_nor nor zero_detect_2_3_nor) after 2 ns; zero <= not(r_int(31)) when m = "1010" else not(r_int(31)) when m = "1011" else --not(zero_detect_int(0) or zero_detect_int(1) or zero_detect_int(2) or zero_detect_int(3)) after 10 ns; --behavioral for zero detect 32 bit (zero_detect_0_1_or nor zero_detect_2_3_or) after 2 ns; result(31 downto 1)<= "0000000000000000000000000000000" when m = "1010" else -- sets upper 31 bits to 0 for slt operations "0000000000000000000000000000000" when m = "1011" else r_int(31 downto 1); result(0) <= r_int(31) when m = "1010" else -- carries msb to lsb for slt operations r_int(31) when m = "1011" else r_int(0); c_in_int <= '1' when m = "0010" else -- puts c_in of 1 into LSB for subtraction '1' when m = "0011" else '1' when m = "1010" else '1' when m = "1011" else '0'; end alu32_structure;